Using Virtual Lines to Enchance Locality Exploitation

Because the spatial locality of numerical codes is sig-niicant, the potential for performance improvements is important. However, large cache lines cannot be used in current on-chip caches because of the important pollution they breed. In this paper, we propose a hardware design, called the Virtual Line Scheme, that allows the utilization of large virtual cache lines on when fetching data from memory for better exploitation of spatial locality, while the actual physical cache line is smaller than currently found cache lines for better exploitation of temporal locality. Simulations show that a 17% to 64% reduction of the average memory access time can be obtained for a 20-cycle memory latency. It is also shown how simple software informations can be used to signiicantly decrease memory traac, a aw associated with the utilization of both large physical or large virtual cache lines.